1. Field of the Invention
The present invention relates to an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes; and, more particularly, to an apparatus and method for decoding a LDPC code based on prototype parity check matrixes which performs decoding at high-speed while reducing complexity by sequentially performing a partial parallel process on the parity check matrix based on multiple prototype parity check matrixes determined according to a parallelization figure in decoding an input bit based on the parity check matrix, to thereby support the length and the bit rate of diverse code words.
This work was supported by the IT R&D program for MIC/IITA [2006-S-002-02, “IMT-Advanced Radio Transmission Technology with Low Mobility”].
2. Description of Related Art
A transmitted signal on a wired/wireless communication system passes through noise, interference and fading on transmission channel. Accordingly, a case that a receiver cannot demodulate the transmitted signal occurs.
An error correction code technique is a representative technique among diverse techniques for reducing error rates which increases due to a fast transmitted speed on the wired/wireless communication system. Recently, the error correction code is applied to most wireless communication systems. In particular, a Low Density Parity Check (LDPC) code of the error correction codes has superior error correction performance and can realize a high-speed decoder at low complexity. Therefore, the LDPC code is the limelight of the error correction code for a next generation high-capacity wireless communication system.
The LDPC code is introduced by “Gallager”. The LDPC code is defined as a parity check matrix where the minimum number of elements has a value ‘1’ and most elements have a value ‘0’.
The LDPC code is divided into a regular LDPC code and an irregular LDPC code. The regular LDPC code is an LDPC code suggested by “Gallager” where all rows in the parity check matrix have values ‘1’ of the same number as an element and all columns have values ‘1’ of the same number as an element. Differently from this, in the parity check matrix of the irregular LDPC code, there are rows including values ‘1’ of different numbers or columns including values ‘1’ of different numbers. It is known that the irregular LDPC code is superior to the regular LDPC code in an error correcting function.
“Fossorier” suggests a Quasi-cyclic LDPC code showing the element of the parity check matrix as a cyclic shifted identity matrix and ‘0 matrix’, not as the elements ‘0’ and ‘1’ on matrix.
Meanwhile, there are a decoding method using a serial or partial parallel processing method and a decoding method using a parallel processing method as a decoding method using the LDPC code.
The serial or partial parallel processing method has a merit that a hardware size for driving is reduced by repeatedly using a few public variable node process blocks and public check node process blocks. However, the serial or partial parallel processing method has a shortcoming that high-speed decoding cannot be supported.
On the other hand, the parallel processing method can support high-speed decoding by performing parallel information exchange by equipping the variable node process block and the check node process block optimized to each parity check matrix. However, the parallel processing method has a shortcoming that the hardware size for driving is large and the hardware size increases as diverse code rates are supported.
Meanwhile, in order to apply Modulation and Coding Scheme (MCS) which is adaptive to the channel status, the wired/wireless communication system is required to use the error correction code having a variable information length and a variable code rate. Accordingly, the conventional decoding methods for supporting diverse and adaptive modulation and coding levels include a method for individually realizing an optimized decoder according to each information length and protection rate and a method for applying information shortening technique or punching technique while using one hardware.
The method for individually realizing the optimized decoder has a shortcoming that the hardware size increases. On the other hand, the information shortening technique or punching technique has a problem that the error correction performance of the LDPC code may be deteriorated by randomly applying the information shortening technique or the parity punching technique.
As described above, the decoding method of the parallel processing method is advantageous to a super high-speed wireless communication system requiring a process speed of several-giga class. Also, In order to efficiently apply the adaptive modulation and coding technique which is popular in the super high-speed wireless communication system, the LDPC code of the variable information length and variable protection rate having superior error correction performance is required. Also, the decoding complexity of the LDPC code should be low.
However, the decoding method of the conventional parallel processing method has a problem that a process time is delayed by increase of calculation quantity and complexity due to random and complex connection between the variable node and the check node. In particular, there is a problem that it is difficult to adaptively correspond to the change of the length and the bit rate of the code word since the calculation quantity and the complexity increases to support the diverse code word lengths and the diverse bit rates in the decoding method of the conventional parallel processing method.